module sys_reset_ctrl(
                input   wire            sclkin,
                output  wire            resetb,
                output  reg             reset_phy
                );

reg     [23:0]       reset_count=24'h00;                

always@(posedge sclkin)
        if(reset_count[23]==1'b0)
                reset_count<=reset_count+1;        

always@(posedge sclkin)
	if(reset_count[23:22]==2'b00)
		reset_phy<=1;
	else
		reset_phy<=0;
		
assign  resetb=reset_count[23];

endmodule